Tunnel FETs have shown to be an alternative transistor design applicable to very low voltage operations. TFETs are a different type of transistor than conventional, thermal MOSFETs, because in TFETs a tunnel energy barrier is modulated at the source region, as opposed to a thermal barrier at the source region. It is the modulation of this tunnel barrier (in particular, a band-to-band tunnel (BTBT) barrier) which results in a drain-current-to-gate-voltage sensitivity (i.e, sub-threshold swing or SS) which can be superior to that in thermal MOSFETs. In thermal MOSFETs, the thermal limit for SS is defined as n*k*T*ln(10), where k is Boltzman's constant, T is the temperature (in Kelvin scale), and n is the ideality factor (greater than or equal to 1, but ideally 1). Under ideal conditions at room temperature, the SS limit for thermal MOSFETs is 60 mV/decade, i.e., the minimum change in gate bias needed to increase the drain current by a factor of 10 is 60 mV. Any device that can offer a room temperature SS limit below 60 mV/decade will permit scaling down the transistor threshold voltage (Vt), and therefore the power supply voltage (VDD) without increasing the off-state leakage current. This is desirable from a circuit design standpoint, since VDD scaling reduces dynamic power consumption while keeping the off-state leakage constant results in no increase in standby power consumption.
TFETs of various designs have achieved both in theory and in practice SS values below 60 mV/dec. This is accomplished by leveraging the energetic distribution of tunnel carriers between the conduction and valence band edges. In order to obtain BTBT, the conduction band of one portion of the device must exist at a lower energy than the valence band of another portion. This is referred to as band edge overlap. The extent of this band edge overlap defines the energy range over which carriers can tunnel between the conduction and valence bands in these regions. The energetic distribution of the tunnel carriers plays a major role in determining SS, since the low SS achieved in TFETs is defined by the transition between zero or negative band edge overlap (i.e, zero BTBT) and some finite band edge overlap (i.e, finite BTBT). This can be engineered through the use of different materials (e.g., Si, Ge, III-V) and/or geometries (e.g., 1-D, 2-D, or 3-D density of states).
A conventional Ge source region achieving sub-60 mV/dec SS in a TFET structure has been empirically demonstrated and shown to significantly improve the performance over prior work due to a reduced bandgap of Ge relative to Si or SiGe. The placement of the Ge source under the gate electrode has been shown by performing an isotropic etch to undercut the gate followed by a Ge deposition to fill the etched region. The limitation of the improvement is mainly related to the use of an isotropic etch to undercut the gate electrode. Since it is desirable to place the Ge directly under the gate dielectric, the gate dielectric ends up being exposed to the isotropic etch, exposing to damage the gate dielectric and lead to high gate leakage. Additionally, there is also a challenge of accurately controlling the undercut etch, since the extent of gate overlap of the Ge source region will determine how much BTBT can be modulated. This tends to occur when the design is a “vertical” TFET (also referenced to a transverse TFET) due to most of the BTBT current flowing in a direction that is transverse to the gate electrode over the source region. In such a design, the total BTBT current is linearly proportional to the extent of gate overlap of the source region.
The concept of a broken-gap TFET has been introduced to effectively engineer the materials on both sides of the BTBT barrier such that a band edge offset exists in equilibrium (i.e, without any gate bias-induced band edge offset), known as a type-III junction. In this particular design, the broken gap region exists at a distance sufficiently away from the gate electrode such that it is not under the influence of the gate electrode. The purpose thereof is to create a TFET structure wherein SS is independent of gate bias, unlike the aforementioned illustration wherein SS changes with the gate bias. Engineering the BTBT barrier effectively is not easily achieved in order to obtain that the tunnel probability in the band edge overlap region be effectively 100%. The remainder of the device is preferably a conventional thermal MOSFET, and such that the structure as a whole is basically a source-limited thermal MOSFET, wherein the thermal barrier modulated by the gate electrode controls the portion of the energetic distribution of carriers injected at the source BTBT barrier. This achieves a very steep SS over several decades of current when compared to the performance of similarly-scaled thermal MOSFETs. The limitation of this embodiment is that no integration scheme is forthcoming for actually building the device.
Conventional TFETs with doped regions have been shown to be formed vertically rather than laterally, (horizontally) as known, for instance in typical MOSFETs, with the gate electrode wrapping around the sidewall regions. A delta-doped p+ SiGe layer exists between the p+ Si source and undoped body regions to facilitate a BTBT injection, and therefore improving the performance. An advantage is that the doped regions can be arbitrarily thick or thin and defined precisely by epitaxial growth. The limitation with this device structure is the same as with all other “vertical” transistor designs, wherein the gate-to-source parasitic capacitance is very high, due to the gate electrode and source regions both covering the same, large, area.
The use of a raised Ge source in a TFET structure is known. The operational concept is the same as previously described except that here, employing a raised source offers a few advantages. Firstly, the presence of the bottom gate corner adjacent to the raised source improves the device electrostatics by suppressing drain field penetration into the gate-induced depletion region in the source (wherein BTBT occurs). Secondly, by using a raised source, precludes the need to use of a required isotropic etch, and so the gate-to-source overlap can be more accurately controlled with epitaxy. However, this structure is limited by the described integration scheme, wherein the Ge epitaxy is formed against the dielectric sidewall region. It is well-known that semiconductor epitaxy against a dielectric sidewall (e.g., raised source/drain epitaxy in conventional MOSFETs) results in faceting and reduced epitaxial film quality along the dielectric sidewall. In the context of a TFET, this will lead to a significant degradation in performance due to the presence of crystalline defects in the epitaxial region.
Referring to FIG. 1a, a planar TFET structure is illustrated operating in a “vertical” (also referred to as transverse) mode. The source and drain regions can be oppositely doped, and the body region doped to the same polarity as the source region. For example, for an n-type TFET, the source and body can be p-type and the drain, n-type. If the source is doped “low” (e.g., 1E19 cm−3), and the body is doped “high” (e.g., 1E18 cm−3), then the dominant BTBT direction will be vertical, or transverse to the gate dielectric boundary to the source.
Referring to FIG. 1b, if the source is doped heavily (e.g., 1E20 cm−3) and the body is doped lightly, (e.g., 1E16 cm−3), then the dominant BTBT direction will be “lateral” (also referenced as longitudinal), or in the direction of the current flow in the channel under the gate dielectric. This is caused by the relative doping levels in the source and body regions that determine which BTBT mode turns on first. With high source doping and low body doping, the lateral BTBT threshold voltage (Vt) will be lower, while the vertical BTBT Vt will be higher, leading to a lateral-BTBT dominated mode of operation, and vice versa.
The lateral and vertical terminologies are only accurate for simple, planar structures. However, when the source region becomes elevated, the orientation of BTBT is altered, since now it is the gate sidewall that controls the BTBT current. This is illustrated with reference to FIG. 1c, wherein the tunnel mode is transverse (as in FIG. 1a), but the tunnel direction is lateral (as in FIG. 1b). The tunnel mode being an essential feature of the type of the TFET, the mode of operation is therefore defined as either transverse (i.e., “vertical” in a planar structure) or longitudinal (i.e., “lateral” in a planar structure).
Although TFETs are known in the art, there is a need for a structure provided with an intrinsic epitaxial layer bridging the source, body and drain regions (p-i-n junctions) of the device structure.